It is known to use a gate array in order to produce a digital integrated circuit having a desired digital circuit with a short lead time. A gate array is a chip on which a large number of basic cells, such as transistors and logic circuit elements, are arranged in an array. By forming an interconnection pattern thereon that matches a user desired digital circuit, the desired digital integrated circuit can be easily produced.
FIG. 1 is a diagram illustrating an example in which an interconnection pattern is formed to interconnect four basic cells in a gate array. In the example of FIG. 1, two PMOS basic cells PMOSC1s and two NMOS basic cells NMOSC1s are arranged in close proximity to each other. Each PMOS basic cell PMOSC1 has a P-type diffusion region PREG1 and two polysilicon gates POLYGs formed on the PREG1. A P-type transistor drain region DRAIN is formed between the two POLYGs, and P-type transistor source regions SOURCEs are formed on the outer sides of the two POLYGs. That is, two PMOS transistors can be formed within this basic cell. Each NMOS basic cell NMOSC1 has an N-type diffusion region NREG1 and two polysilicon gates POLYGs formed on the NREG1. An N-type transistor drain region DRAIN is formed between the two POLYGs, and N-type transistor source regions SOURCEs are formed on the outer sides of the two POLYGs. That is, two transistors can be formed within this basic cell. An N-type diffusion region NREG1 is formed is formed between the adjacent PMOSC1s, while a P-type diffusion region PREG1 is formed between the adjacent NMOSC1s. The gate electrodes POLYGs, drain regions DRAINs, source regions SOURCEs, and inter-device diffusion regions PREG1, NREG1 of the respective basic cells PMOSC1s and NMOSC1s are interconnected by metal interconnect lines METAL1s and contacts CONT1s.
A large number of basic units comprising such PMOSC1s and NMOSC1s are arranged in an array.
In the example of FIG. 1, two transistors can be formed in each of the basic units PMOSC1s and NMOSC1s, but in an alternative example, only one transistor can be formed. The two transistors in each basic unit may be used as transistors that perform the same operation in order to double the driving capability, but alternatively, they can be configured as two independent transistors. When using the transistors to perform the same operation, the drain region is common to the transistors, and the two gate electrodes and the two source regions, respectively, are electrically connected to each other. On the other hand, when configuring them as two independent transistors, at least either the two gate electrodes or the two source regions are not electrically connected to each other. In this way, the two transistors in each of the basic units PMOSC1s and NMOSC1s are basically formed on the assumption that they are used independently of each other.
Gate arrays for digital circuits are well known, and will not be discussed in detail here.
In recent years, it has been desired to increase the level of integration of analog circuits and to produce them with a short lead time.
A digital circuit need only output or operate with a binary signal having a level falling within a predetermined range and representing a 0 or a 1, and a circuit that operates properly can be easily produced if manufacturing errors are held within prescribed limits. On the other hand, in analog circuits, analog signal values such as voltage values and current values directly affect the circuit operation and output. As a result, analog circuits have had the problem that they are susceptible to differences in device characteristics caused by manufacturing errors. It has therefore been common practice to design each individual analog circuit according to the desired specification and to make adjustments at the manufacturing stage to achieve the production of the desired circuit.
In analog circuits, transistor characteristics differ according to the location of placement, due to such factors as ion implantation profiles and oxide film thickness profiles during manufacturing. A layout scheme called common centroid layout is known for compensating for such differences in characteristics. For example, if there is a difference in the characteristics of two transistors forming a differential pair in a differential amplifier, the error of the analog circuit increases; therefore, the two transistors forming such a differential pair are arranged in a common centroid configuration.
FIG. 2 is a diagram illustrating a common centroid layout example of a differential pair of P-type transistors. The first P-type transistor PMAD1 forming one of the differential pair transistors comprises PMAD1A and PMAD1B, and the second P-type transistor PMAD2 forming the other differential pair transistor comprises PMAD2A and PMAD2B. PMAD1A and PMAD1B are arranged diagonally opposite each other, and PMAD2A and PMAD2B are also arranged diagonally opposite each other, the four transistors thus forming the vertices of a rectangle. The source regions of the four P-type transistors PMAD1A, PMAD1B, PMAD2A, and PMAD2B are connected together by metal interconnect lines NDSA and NDSB on first and second layers, respectively, contacts CONT1s, and plated-through holes VIA1s. The drain regions of the two P-type transistors PMAD1A and PMAD1B are connected to a first output via metal interconnect lines NDD1A and NDD1B, contacts CONT1s, and plated-through holes VIA1s. The drain regions of the two P-type transistors PMAD2A and PMAD2B are connected to a second output via metal interconnect lines NDD2A and NDD2B, contacts CONT1s, and plated-through holes VIA1s. The gate electrodes of the two P-type transistors PMAD1A and PMAD1B are connected to a first input via a metal interconnect line IMOP1 and contacts CONT1s. The gate electrodes of the two P-type transistors PMAD2A and PMAD2B are connected to a second input via a metal interconnect line IPOP1 and contacts CONT1s.
When the two transistors forming the differential pair are each formed from two transistors and arranged in a common centroid configuration, as illustrated in FIG. 2, the difference in the characteristics of the two transistors forming the differential pair can be reduced by compensating for the effects of such factors as ion implantation profiles and oxide film thickness profiles.
Another factor known to adversely affect transistor matching is the antenna effect.
The antenna effect refers to a phenomenon in which, during a process (fabrication process) using a plasma for the fabrication of a MOS transistor, an electrical stress is applied to the gate oxide film of the MOS transistor because of the presence of electric charges in the plasma, leading to a reliability problem or causing the characteristics of the MOS transistor to change. When processing the metal interconnect line connected to the gate oxide film, the metal interconnect line being processed acts as an antenna and gathers electric charges, which can damage the gate oxide film; therefore, this phenomenon is generally called the antenna effect.
It is pointed out that, due to the electric charges gathered by the antenna (the metal interconnect line connected to the gate) during the processing of the metal interconnect line in the plasma process, the threshold voltage Vth of the MOS transistor changes, and matching between the MOS transistors forming a differential pair degrades due to unevenness in the antenna effect.
To alleviate the stress applied to the MOS transistor due to the antenna effect, a method is known in the prior art that inserts a diode called an antenna diode into the gate node of the MOS transistor to be protected.
The antenna diode acts as a current discharge path during the processing of the metal interconnect line in the plasma process, and has the function of preventing possible damage to the gate oxide film. During normal operation after the manufacture, this diode is reverse biased so that it has hardly any effect on the operation, though it induces a small amount of leakage current and an increase in capacitance and area.
It is known that the threshold voltage Vth of a MOS transistor changes when an interconnect line is present above the channel of the transistor than when it is not.
Broken bonds known as dangling bonds exist at the interface between the channel and gate oxide film of the MOS transistor, because the crystal structure abruptly changes across the interface. Since the dangling bonds act as carrier traps, it is desirable to terminate the dangling bonds with hydrogen. If a metal interconnect line is present directly above the channel, it may prevent hydrogen from reaching the channel interface in the annealing step which works to terminate the dangling bonds with hydrogen at the end of the fabrication process. It is therefore desirable that no interconnect lines be provided on MOS transistors that need matching. Otherwise, between the transistors that need matching, the entire structure including the interconnect line above the channel of the MOS transistor must be formed in the same geometry.